LAB_6. Maquina de estados 3.

LAB_6. Máquina de estados tipo Mealy y Moore

LAB_6. Código en Xilinx de la máquina de estados

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity maquina_2 is
port (
 car: in  STD_LOGIC;
           timed: in STD_LOGIC;
 starttimer: out STD_LOGIC;
           majorgreen , minorgreen : out  STD_LOGIC;
 clk : in STD_LOGIC;
 reset : in STD_LOGIC);
       
end maquina_2;

architecture Behavioral of maquina_2 is


type estado is (s1,s2,idle);
signal nextstate , currentstate :estado;
--signal  starttimer: std_logic;
begin
process (car,timed,currentstate)
begin
starttimer <='0';

case currentstate is
when idle =>
nextstate <= s1;
when s1 =>
majorgreen <='1';
minorgreen <='0';
if car ='1' then
starttimer <='1';
nextstate<= s2;
else
nextstate <=s1;
end if;
when s2 =>
majorgreen <='0';
minorgreen <='1';
if timed ='1' then
nextstate<= s1;
else
nextstate<=s2;
end if;

end case;
end process;

FFs: process (clk, reset)
begin
if reset = '1' then
currentstate <= idle;
elsif clk'event and clk='1' then
currentstate <= nextstate;
end if;
end process;
end Behavioral;