LAB_7. Maquina de estados 4.

LAB_7. Máquina de estados tipo Registro de salidas

LAB_7. Código en Xilinx de la máquina de estados

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity maquina_4 is

port (

 a: in  STD_LOGIC;

           b : in STD_LOGIC;

           y : out  STD_LOGIC_vector (2 downto 0);

 clk : in STD_LOGIC;

 reset : in STD_LOGIC);

       

end maquina_4;

architecture Behavioral of maquina_4 is

type estado is (s1,s2,s3,s4,s5,idle);

signal nextstate , currentstate :estado;

begin

siguiente : process (a,b,currentstate)

begin

case Currentstate is 

when idle=>

Nextstate <= s1;

when s1 =>

if a ='1' then 

Nextstate <= s2;

else

Nextstate <= s1;

end if;

When s2=>

if a ='0' and b = '1' then

Nextstate <=s3;

elsif a ='1' and b = '1' then

Nextstate <= s4;

elsif a ='1' and b = '0' then

Nextstate <= s5;

else Nextstate <= s2;

end if;

when s3 =>

Nextstate <= s4;

when s4 => 

nextstate <= idle;

when s5 => 

nextstate <= idle;

end case;

end process;

FFs: process (clk, reset)

begin

if reset = '1' then

currentstate <= idle;

elsif clk'event and clk='1' then

currentstate <= nextstate;

end if;

end process;

output : process (clk,reset)

begin 

if reset = '1'then

y <= "000";

elsif clk'event and clk='1' then

case nextstate is 

when idle => 

y <= "000";

when s1 => 

y <= "101";

when s2 => 

y <= "111";

when s3 => 

y <= "011";

when s4 => 

y <= "000";

when s5 => 

y <= "100";

end case  ; 

end if;

end process;

end Behavioral;